Semiconductor chips, commonly referred to as “integrated circuits” are an essential component of electronic devices, such as cell phones, personal computers and personal entertainment devices. These chips are usually mounted on a platform which is also equipped with terminals for the electrical connectivity with the external world. The platform could be either a single layer metal leadframe or a multi-layer printed wire board or a structure of similar function. Besides providing means for external electrical connectivity, these platforms also provide mechanical support to the chips. Encapsulation ensures protection of the chip from harsh physical and environmental factors. The interconnection between the chip and its supporting platform is commonly referred to as “first level” assembly. Several approaches exist for the first level assembly of chip to a supporting platform. These include so called “Wire-bonding”, “Tape Automated Bonding (TAB)” and “Flipchip” approaches.
The approach for the first level connection between the chip and the platform has strong ramifications on the overall package size, performance and reliability. In an electronic device circuit, several packages are interconnected using a common printed circuit board. A large package size increases the distance between chips or between each chip and other elements of the circuit. These larger distances result in longer delays in the transmission of electrical signals between chips. Consequently, the entire electronic device is slowed down.
The approach used for the first level assembly of the chip to the platform also influences the capacitances and inductances associated with the chip-to-platform connections. Interconnections which result in large values of capacitances and inductances may result in large signal transmission delays, large switching noise and therefore performance degradation. Thus, lowering the capacitive and inductive parasitics associated with first level assembly is highly desirable.
Wire-bonding ordinarily can only be employed when the chip I/O pads are distributed along the periphery of the chip and the substrate connection pads surround the chip in a ring-like configuration. For circuits which involve simultaneous switching of a large number of gates, as is the case in present generation of microprocessors, high inductances of the wire bonds lead to a large switching noise. Wire bonds usually fan out from the chip to the platform. Therefore, overall package size increases considerably relative to the chip size. Therefore, from the electrical noise and compactness standpoint, wire-bonding does not provide an optimal first level assembly process.
Tape automated bonding (TAB) requires a flexible tape with metal leads mounted on a polymer film. Usually, the tape leads fan out from the chip pads to the platform connection pads. Therefore, the package is considerably larger than the chip. The flexible tape represents a new layer for interconnection and considerably adds to the cost of the package. This is an additional process step and requires processes similar to those used for IC fabrication such as lithography and etching. The chips are bonded to a flexible tape which contains metal traces for external connectivity. Usually all the leads are bonded simultaneously to the chip pads in what is referred as “Gang Bonding” process. This requires very tight control of the planarity of the tape leads and the chip pads connection sites. From a mechanical stress standpoint, flexible tape represents a good solution because the tape can deform and absorb the stress thereby increasing the reliability of the joints.
In a flipchip process, usually the I/O pads are distributed on the entire surface of the chip. This enables placement of a larger number of I/O pads at an increased pitch without increasing the size of the silicon chip. The I/O pads are deposited with metal bumps of materials which can melt at bonding temperatures and fuse with the substrate pad materials. The chip is bonded face-down such that the active face of the chip with the connection pads faces the top surface of the substrate. The metal bumps on the chip pads provide a separation between the chip and the substrate. Therefore, inductances associated with these bumps are considerably lower than a wire-bond or a TAB lead. An epoxy resin material is dispensed in the region between the chip and the substrate. This so called “underfill” material encapsulates the exposed regions of the metallic joints and acts as a stress buffer thereby significantly improving the reliability. However, this underfilling step is an additional process and adds to the assembly cost by increasing the process cycle time as well as the number of constituent layers.
Thus, a need still remains for an economical and reliable assembly process that allows small package size and the possibility of multiple packages in a single package. In view of the rigorous economic demands and system performance requirements, it is increasingly critical that answers be found to these problems. Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.